Worked on the Cheshire project repository to enhance the reliability of Xilinx FPGA targets by addressing system reset handling. Focused on hardware design and FPGA development, the work involved implementing conditional logic in SystemVerilog to define the sys_rst signal when USE_RESET or USE_RESETN directives were absent. This approach prevented potential read-in issues and ensured correct reset sequencing across various build configurations. By refining the reset mechanism, the changes led to more robust startup behavior and reduced configuration-specific bugs, while also simplifying future maintenance. The contribution demonstrated careful attention to detail in hardware design and practical application of Verilog/SystemVerilog skills.