OpenXiangShan-Nanhu/Nanhu-V5
Nov 2024 – Jun 2025
3 Months active
Languages Used
ChiselScala
Technical Skills
CPU ArchitectureCPU DesignComputer ArchitectureHardware DesignRISC-VRISC-V Architecture
Jinghui-Z
PROFILE
Jinghui-z
Worked on the OpenXiangShan-Nanhu/Nanhu-V5 repository, focusing on CPU core and cache subsystem improvements over three months. Enhanced instruction fetch reliability by refactoring the Front-End Queue and tuning branch prediction logic, using Chisel and Verilog to streamline FTQ state and reduce mispredictions. Improved pipeline robustness by duplicating validation registers and refining ICache timing to prevent stalls during flushes, leveraging digital logic design and timing analysis. Addressed race conditions in CPU flush logic by simplifying BPU flush handling and distinguishing between IFU and backend cache flushes, which stabilized redirect behavior and improved cache coherence across diverse workloads in RISC-V architecture.
Overall Statistics
Feature vs Bugs
40%Features
Repository Contributions
8Total
Bugs
3
Commits
8
Features
2
Lines of code
863
Activity Months3
Your Network
20 peopleShared Repositories
20
linmingfengMember
happpy-codeMember
luguangyangMember
denghaiwenMember
zhangbinMember
zhuhangMember
cai weipengMember
chen kangpingMember
chen kangpingMember
Work History
June 2025
2 Commits
Jun 1, 2025June 2025 (OpenXiangShan-Nanhu/Nanhu-V5): CPU flush logic correctness improvements focusing on reducing race conditions and invalidations during redirects. Implemented targeted fixes: removed redundant BPU flush logic in the IFU and refined ICache flush behavior to distinguish IFU vs backend paths, preserving softPrefetches during IFU redirects. Result: stabilized redirect handling, improved cache coherence, and reduced flush-related overhead across workloads.
2 Commits
Jun 1, 2025June 2025 (OpenXiangShan-Nanhu/Nanhu-V5): CPU flush logic correctness improvements focusing on reducing race conditions and invalidations during redirects. Implemented targeted fixes: removed redundant BPU flush logic in the IFU and refined ICache flush behavior to distinguish IFU vs backend paths, preserving softPrefetches during IFU redirects. Result: stabilized redirect handling, improved cache coherence, and reduced flush-related overhead across workloads.
June 2025
January 2025
2 Commits • 1 Features
Jan 1, 2025January 2025 monthly summary for OpenXiangShan-Nanhu/Nanhu-V5. Focused on delivering robust IFU behavior and stabilizing the ICache path under flush conditions, with clear commit traceability.
January 2025
2 Commits • 1 Features
Jan 1, 2025January 2025 monthly summary for OpenXiangShan-Nanhu/Nanhu-V5. Focused on delivering robust IFU behavior and stabilizing the ICache path under flush conditions, with clear commit traceability.
November 2024
4 Commits • 1 Features
Nov 1, 2024Month: 2024-11 | Repository: OpenXiangShan-Nanhu/Nanhu-V5 Focused on core FTQ optimization and branch-prediction stability to boost instruction fetch efficiency and runtime reliability. Deliverables emphasize business value through cleaner FTQ logic, reduced mispredictions, and actionable traceability.
4 Commits • 1 Features
Nov 1, 2024Month: 2024-11 | Repository: OpenXiangShan-Nanhu/Nanhu-V5 Focused on core FTQ optimization and branch-prediction stability to boost instruction fetch efficiency and runtime reliability. Deliverables emphasize business value through cleaner FTQ logic, reduced mispredictions, and actionable traceability.
November 2024
Activity
Loading activity data...
Quality Metrics
Correctness81.2%
Maintainability81.2%
Architecture80.0%
Performance77.6%
AI Usage20.0%
Skills & Technologies
Programming Languages
ChiselScala
Technical Skills
CPU ArchitectureCPU DesignCache CoherenceCache CoherencyComputer ArchitectureDigital Logic DesignHardware DesignRISC-VRISC-V ArchitectureTiming AnalysisVerilog/ChiselVerilog/SystemVerilog (implied by context)
Repositories Contributed To
Overview of all repositories you've contributed to across your timeline