Worked on the riscv/zibi repository to deliver BEQI and BNEI conditional branch instruction support for the Zibi extension, targeting the 0.6 release. This involved designing instruction set enhancements that enable register-immediate comparisons, using a 12-bit signed immediate encoding in the B-type format to reduce register pressure and improve branch efficiency in common code paths. The work included comprehensive updates to release documentation, ensuring clarity for downstream integration and customer adoption. Maintained a disciplined workflow with clear commit history and draft tracking. Utilized EDN and adoc languages, applying skills in documentation, instruction set design, and RISC-V architecture throughout the process.