Liangsen contributed to the OpenXiangShan-Nanhu/LinkNan repository, developing and maintaining a complex RISC-V SoC platform with a focus on hardware-software integration, FPGA flows, and system configurability. He engineered features such as asynchronous clock domain crossing, AXI protocol enhancements, and robust build automation, using Chisel, Verilog, and Scala to implement scalable cluster topologies and optimize memory subsystems. Liangsen’s work included extensive simulation infrastructure, device tree generation, and dependency management, ensuring reliable validation and streamlined releases. His approach emphasized maintainability and performance, addressing timing, power, and verification challenges while supporting evolving requirements through disciplined code organization and continuous integration.
November 2025 (2025-11) – OpenXiangShan-Nanhu/LinkNan: dependency hygiene and build stability focus. The primary deliverable this month was updating a subproject dependency (zhujiang) to a newer commit hash; no functional code changes were required. No major bugs addressed in this period. The update improves build reproducibility, compatibility with the latest Zhujiang changes, and reduces risk from outdated dependencies. Skills demonstrated include dependency management, version control discipline, and proactive maintenance of third-party integrations to support upcoming work.
November 2025 (2025-11) – OpenXiangShan-Nanhu/LinkNan: dependency hygiene and build stability focus. The primary deliverable this month was updating a subproject dependency (zhujiang) to a newer commit hash; no functional code changes were required. No major bugs addressed in this period. The update improves build reproducibility, compatibility with the latest Zhujiang changes, and reduces risk from outdated dependencies. Skills demonstrated include dependency management, version control discipline, and proactive maintenance of third-party integrations to support upcoming work.
In 2025-10, OpenXiangShan-Nanhu/LinkNan focused on stabilizing memory interface behavior and keeping dependencies up to date to support ongoing feature work and performance goals. The month delivered targeted memory system tuning and maintained codebase health through subproject updates, enabling smoother future integrations and throughput stability.
In 2025-10, OpenXiangShan-Nanhu/LinkNan focused on stabilizing memory interface behavior and keeping dependencies up to date to support ongoing feature work and performance goals. The month delivered targeted memory system tuning and maintained codebase health through subproject updates, enabling smoother future integrations and throughput stability.
Month: 2025-09 - OpenXiangShan-Nanhu/LinkNan: Delivered broad dependency hygiene, FPGA configurability improvements, and stability fixes across modules to drive platform readiness for the next release. Highlights include coordinated submodule and dependency bumps, expanded FPGA configurability (DDR delays, memory range controls, JTAG/DMA exposure), PCIe MST support, 16G PMEM, and numerous port naming/connection fixes, plus release automation and script updates across nanhu, difftest, and zhujiang.
Month: 2025-09 - OpenXiangShan-Nanhu/LinkNan: Delivered broad dependency hygiene, FPGA configurability improvements, and stability fixes across modules to drive platform readiness for the next release. Highlights include coordinated submodule and dependency bumps, expanded FPGA configurability (DDR delays, memory range controls, JTAG/DMA exposure), PCIe MST support, 16G PMEM, and numerous port naming/connection fixes, plus release automation and script updates across nanhu, difftest, and zhujiang.
OpenXiangShan-Nanhu/LinkNan - 2025-08 monthly highlights focusing on startup safety, system timing, PCIe/NC memory simulation, and maintenance to support long-term stability and performance. Key outcomes include robust PPU legality checks, safer power-on CPU enable states, and improvements to simulation initialization logic (initial attempt to initialize regs at startup followed by a revert to maintain stable simulation). System clock and reset wiring for the ST wrapper was added to improve timing determinism. Simulation memory modeling was enhanced with expanded PCIe memory and a map-based NC memory representation for scalability and test coverage. Ongoing maintenance included comprehensive dependency and submodule bumps to align toolchains and reduce drift. Key contexts: - Features delivered across PPU, CPU, ST wrapper, and simulation layers. - Notable bug fix patterns in NC memory modeling to improve reliability. - Maintenance-driven changes to keep dependencies current.
OpenXiangShan-Nanhu/LinkNan - 2025-08 monthly highlights focusing on startup safety, system timing, PCIe/NC memory simulation, and maintenance to support long-term stability and performance. Key outcomes include robust PPU legality checks, safer power-on CPU enable states, and improvements to simulation initialization logic (initial attempt to initialize regs at startup followed by a revert to maintain stable simulation). System clock and reset wiring for the ST wrapper was added to improve timing determinism. Simulation memory modeling was enhanced with expanded PCIe memory and a map-based NC memory representation for scalability and test coverage. Ongoing maintenance included comprehensive dependency and submodule bumps to align toolchains and reduce drift. Key contexts: - Features delivered across PPU, CPU, ST wrapper, and simulation layers. - Notable bug fix patterns in NC memory modeling to improve reliability. - Maintenance-driven changes to keep dependencies current.
July 2025: FPGA-centric delivery and maintenance across the LinkNan repo (OpenXiangShan-Nanhu/LinkNan) delivering stronger multi-core FPGA configurations, expanded hardware interfaces, and improved build stability. Key work focused on enabling quad-core operation, refining timing and domain crossing, and stabilizing SV/DFT-friendly flows, while maintaining a strong emphasis on business value through reliability, scalability, and maintainability.
July 2025: FPGA-centric delivery and maintenance across the LinkNan repo (OpenXiangShan-Nanhu/LinkNan) delivering stronger multi-core FPGA configurations, expanded hardware interfaces, and improved build stability. Key work focused on enabling quad-core operation, refining timing and domain crossing, and stabilizing SV/DFT-friendly flows, while maintaining a strong emphasis on business value through reliability, scalability, and maintainability.
June 2025 monthly summary for OpenXiangShan-Nanhu/LinkNan: Focused on delivering core features, stabilizing the hardware-software integration, and advancing FPGA flow and SoC readiness. Highlights include intrinsic generator implementation, async bridge consolidation, CLI error handling improvements, explicit PCIe address range, and enhanced FPGA floorplanning and timing. These changes improve reliability, scalability, and performance of LinkNan deployments, enabling smoother SoC integration and faster iteration cycles.
June 2025 monthly summary for OpenXiangShan-Nanhu/LinkNan: Focused on delivering core features, stabilizing the hardware-software integration, and advancing FPGA flow and SoC readiness. Highlights include intrinsic generator implementation, async bridge consolidation, CLI error handling improvements, explicit PCIe address range, and enhanced FPGA floorplanning and timing. These changes improve reliability, scalability, and performance of LinkNan deployments, enabling smoother SoC integration and faster iteration cycles.
May 2025 monthly performance overview for OpenXiangShan-Nanhu/LinkNan, focused on delivering business value through feature improvements, reliability fixes, and maintainability enhancements. Key changes target BT IO capabilities, power management, system configurability, and testing/automation workflows, with an emphasis on reducing reset risks, improving hardware generation flows, and keeping dependencies up to date.
May 2025 monthly performance overview for OpenXiangShan-Nanhu/LinkNan, focused on delivering business value through feature improvements, reliability fixes, and maintainability enhancements. Key changes target BT IO capabilities, power management, system configurability, and testing/automation workflows, with an emphasis on reducing reset risks, improving hardware generation flows, and keeping dependencies up to date.
OpenXiangShan-Nanhu achieved a productive April 2025 across LinkNan and Nanhu-V5, delivering a combination of feature work, targeted bug fixes, and substantial maintenance that improves hardware description accuracy, verification speed, and system configurability. Key efforts focused on accelerating SN lookup, stabilizing device-tree and simulation setups, and enhancing testing and build tooling to support faster validation cycles and higher confidence in releases.
OpenXiangShan-Nanhu achieved a productive April 2025 across LinkNan and Nanhu-V5, delivering a combination of feature work, targeted bug fixes, and substantial maintenance that improves hardware description accuracy, verification speed, and system configurability. Key efforts focused on accelerating SN lookup, stabilizing device-tree and simulation setups, and enhancing testing and build tooling to support faster validation cycles and higher confidence in releases.
March 2025 monthly summary for OpenXiangShan-Nanhu/LinkNan: Delivered major integration, performance, and reliability improvements with a focus on dependency modernization, architectural refactors, and tooling enhancements. Achievements span feature delivery, system stability, and measurable business value such as faster test cycles, lower latency, and improved maintainability.
March 2025 monthly summary for OpenXiangShan-Nanhu/LinkNan: Delivered major integration, performance, and reliability improvements with a focus on dependency modernization, architectural refactors, and tooling enhancements. Achievements span feature delivery, system stability, and measurable business value such as faster test cycles, lower latency, and improved maintainability.
February 2025 (OpenXiangShan-Nanhu/LinkNan): Focused on enhancing simulation observability, reliability, and maintainability. Delivered DPI Lua scoreboard support in Verilator, L2 cache performance counters for visibility into memory traffic, and LNTop refinements with a robust IO reset path. Fixed a SimTop reset propagation bug and advanced tooling and dependency stability through Zhujiang/xs-utils updates and config-driven simulation improvements. These efforts deliver tangible business value by accelerating verification, reducing debugging time, and improving build stability.
February 2025 (OpenXiangShan-Nanhu/LinkNan): Focused on enhancing simulation observability, reliability, and maintainability. Delivered DPI Lua scoreboard support in Verilator, L2 cache performance counters for visibility into memory traffic, and LNTop refinements with a robust IO reset path. Fixed a SimTop reset propagation bug and advanced tooling and dependency stability through Zhujiang/xs-utils updates and config-driven simulation improvements. These efforts deliver tangible business value by accelerating verification, reducing debugging time, and improving build stability.
January 2025 (OpenXiangShan-Nanhu/LinkNan) monthly summary: - Key features delivered and improvements: - Chi flit width reduction to optimize CHI interface, reducing area and power while maintaining throughput (commit adfe9e74a1e20d88c715cf9d941dfe2d300b3606). - Refactor SoC hierarchy and add support to select NoC socket of CPU cluster, improving configurability and future scalability (commit 246a0729c06e168dfa6746a62439ddef5eda0308). - Reduce CPU cluster IO to simplify interconnect, lowering wiring complexity and potential bottlenecks (commit 3a2e9fbf16490a882b4f1fa173db9a03f13db725). - Enable asynchronous C2C on sockets for faster inter-socket communication and better parallelism (commit 035512869e65720b62971e6ee57b3f43df10bfda). - FPGA workflow improvement: skip manual Aurora reset to speed up FPGA iterations (commit 321d3f24a9a5f6815d823cbcb097859ccb8d401f). - Major bugs fixed: - Fix compilation error introduced in the batch (commit fbd8f9c8cb381d4a4e4b2d345a7f5a0e2baabb60). - Fix top-level AXI connections to ensure proper interface wiring (commit 9a77f027ec7bb781e071e27997f741e486aa35b7). - Cluster: Default boot address connection fix to ensure reliable boot flow (commit 787611947eabb8c1357d219fb59c81a3e42e1bbe). - Lua SCB: Reset signal wiring fix to ensure proper reset behavior (commit 1e9bb63c5d514b7a2c87d99c8953e54287c05a15). - Lua SCB: L2 path, Uncore path fixes to correct routing and improve stability (commits b0913fd2e0e68be94b149459d860959e7a965e39 and 68af58222ee1f1f0f14f1ab33c1a60e4bd4e73ac). - Maintenance: Bump zhujiang dependencies across the batch for consistency and stability (multiple commits listed in the batch). - Overall impact and accomplishments: - Improved system configurability, reliability, and throughput, enabling faster time-to-market for CPU cluster configurations and interconnects. - Reduced risk in boot and path wiring, with validated reset and path routing across AXI and Lua SCB components. - Streamlined maintenance through dependency bumps (zhujiang, xs-utils) and hardware assertion upgrades. - Technologies and skills demonstrated: - CHI interface optimization, SoC/NoC architectural refactor, asynchronous inter-core communication, AXI/Lua SCB wiring validation, FPGA workflow optimization, hardware assertion adoption, and dependency management.
January 2025 (OpenXiangShan-Nanhu/LinkNan) monthly summary: - Key features delivered and improvements: - Chi flit width reduction to optimize CHI interface, reducing area and power while maintaining throughput (commit adfe9e74a1e20d88c715cf9d941dfe2d300b3606). - Refactor SoC hierarchy and add support to select NoC socket of CPU cluster, improving configurability and future scalability (commit 246a0729c06e168dfa6746a62439ddef5eda0308). - Reduce CPU cluster IO to simplify interconnect, lowering wiring complexity and potential bottlenecks (commit 3a2e9fbf16490a882b4f1fa173db9a03f13db725). - Enable asynchronous C2C on sockets for faster inter-socket communication and better parallelism (commit 035512869e65720b62971e6ee57b3f43df10bfda). - FPGA workflow improvement: skip manual Aurora reset to speed up FPGA iterations (commit 321d3f24a9a5f6815d823cbcb097859ccb8d401f). - Major bugs fixed: - Fix compilation error introduced in the batch (commit fbd8f9c8cb381d4a4e4b2d345a7f5a0e2baabb60). - Fix top-level AXI connections to ensure proper interface wiring (commit 9a77f027ec7bb781e071e27997f741e486aa35b7). - Cluster: Default boot address connection fix to ensure reliable boot flow (commit 787611947eabb8c1357d219fb59c81a3e42e1bbe). - Lua SCB: Reset signal wiring fix to ensure proper reset behavior (commit 1e9bb63c5d514b7a2c87d99c8953e54287c05a15). - Lua SCB: L2 path, Uncore path fixes to correct routing and improve stability (commits b0913fd2e0e68be94b149459d860959e7a965e39 and 68af58222ee1f1f0f14f1ab33c1a60e4bd4e73ac). - Maintenance: Bump zhujiang dependencies across the batch for consistency and stability (multiple commits listed in the batch). - Overall impact and accomplishments: - Improved system configurability, reliability, and throughput, enabling faster time-to-market for CPU cluster configurations and interconnects. - Reduced risk in boot and path wiring, with validated reset and path routing across AXI and Lua SCB components. - Streamlined maintenance through dependency bumps (zhujiang, xs-utils) and hardware assertion upgrades. - Technologies and skills demonstrated: - CHI interface optimization, SoC/NoC architectural refactor, asynchronous inter-core communication, AXI/Lua SCB wiring validation, FPGA workflow optimization, hardware assertion adoption, and dependency management.
December 2024 monthly summary for OpenXiangShan-Nanhu/LinkNan: Delivered a set of Lua scoreboard enhancements, hardware/test reliability improvements, and essential maintenance across dependencies, resulting in richer scoring capabilities, more robust simulation/testing, and streamlined build stability. The work focused on business value through improved observability, parameterization, and reliability for ongoing development and validation. Key improvements span: Lua scoreboard enhancements (parameter passing, debugging, and DCU integration), Boom core enhancements (boot address and randomization), SCB configuration enhancements, and comprehensive dependency maintenance. In addition, several bug fixes stabilized build/test workflows and hardware simulations, reducing risk during platform bring-up and testing cycles.
December 2024 monthly summary for OpenXiangShan-Nanhu/LinkNan: Delivered a set of Lua scoreboard enhancements, hardware/test reliability improvements, and essential maintenance across dependencies, resulting in richer scoring capabilities, more robust simulation/testing, and streamlined build stability. The work focused on business value through improved observability, parameterization, and reliability for ongoing development and validation. Key improvements span: Lua scoreboard enhancements (parameter passing, debugging, and DCU integration), Boom core enhancements (boot address and randomization), SCB configuration enhancements, and comprehensive dependency maintenance. In addition, several bug fixes stabilized build/test workflows and hardware simulations, reducing risk during platform bring-up and testing cycles.
Month: 2024-11 — OpenXiangShan-Nanhu/LinkNan monthly summary: In November 2024, the team delivered key features, fixed critical issues, and strengthened the build, verification, and platform infrastructure. The work focused on business value: improved build reliability and speed, enhanced power-domain control and cluster topology for scalable SoC designs, and strengthened verification fidelity and configuration control for faster validation and safer releases.
Month: 2024-11 — OpenXiangShan-Nanhu/LinkNan monthly summary: In November 2024, the team delivered key features, fixed critical issues, and strengthened the build, verification, and platform infrastructure. The work focused on business value: improved build reliability and speed, enhanced power-domain control and cluster topology for scalable SoC designs, and strengthened verification fidelity and configuration control for faster validation and safer releases.
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