Worked on stabilizing the ChiselDB export process within the OpenXiangShan/Utility repository, focusing on backend development and database management using Scala. Addressed an edge-case bug by implementing logic to explicitly ignore zero-width ports during database generation, ensuring that only valid ports contribute to the resulting database structure. This targeted fix resolved issue #119 and improved the reliability and data integrity of ChiselDB exports, reducing the risk of generation-time errors and downstream failures in hardware design workflows. The work demonstrated careful attention to detail in handling database edge cases and contributed to a more robust and maintainable codebase.