Developed a runtime assertion mechanism for the OpenXiangShan/Utility repository to detect and block SRAM read-write conflicts in operational modes that prohibit such behavior. This feature, implemented in Scala and leveraging expertise in digital logic design and embedded systems, prevents invalid memory interactions from reaching the SRAM macro, thereby reducing the risk of silicon misbehavior. The work included updating and expanding the test suite to validate the new assertion across relevant modes, enhancing both runtime safety and test coverage. By enabling early detection of potential hardware issues, the contribution improved the maintainability and reliability of the Utility component’s hardware design.