Worked on enhancing memory subsystem reliability and core performance by centralizing and enriching SRAM read-write conflict handling in the OpenXiangShan/Utility and OpenXiangShan/XiangShan repositories. Refactored the SRAMTemplate to support multiple conflict resolution strategies, including corrupt reads, buffered writes, and write stalls, while ensuring backward compatibility and comprehensive test coverage. This architectural change reduced frontend complexity and improved instruction per cycle (IPC) and branch prediction accuracy. Leveraged skills in RTL design, memory systems, and test-driven development, utilizing Chisel and Scala to deliver configurable, safer dual-port SRAM operations and measurable performance improvements validated through expanded regression testing.