Worked on the antmicro/verilator repository to enhance the robustness and reliability of finite state machine (FSM) detection logic. Focused on addressing unchecked casts and variable redeclaration issues, the work involved refactoring the FSM detection path to introduce stricter type safety and improved reference handling. Using C++ and leveraging FSM design principles, the changes reduced the risk of incorrect state detection in edge-case scenarios and improved maintainability for future development. Additional efforts included updating documentation and improving code hygiene, supporting ongoing FSM feature work. The approach emphasized careful testing and code quality, contributing to a more stable and reliable codebase.