Worked on expanding hardware support in the ROCm/TransformerEngine repository by delivering a blockwise FP8 quantization and GEMM pathway optimized for AMD ROCm GPUs. This involved porting CUDA kernels and logic to HIP, introducing platform-specific optimizations for gfx942 and gfx950 architectures, and updating tests to validate ROCm-compatible FP8 features. Added preprocessor guards for CDNA3 and CDNA4 architectures to prevent build-time errors on unsupported hardware, improving CI reliability. The work leveraged C++, CUDA/HIP, and GPU programming expertise to broaden deployment options, unlock FP8 performance on AMD GPUs, and strengthen the reliability of quantization workflows across diverse hardware stacks.