Developed and integrated the BR_UNUSED macro for the xlsynth/bedrock-rtl repository to address unused Verilog signal warnings during linting. The solution involved defining a Verilog macro that safely sinks unused signals, then incorporating it into the Bazel-based build system to ensure it would not affect synthesis results. Validation was performed using a basic SystemVerilog testbench, confirming the macro’s intended behavior. This work reduced lint noise in continuous integration and code reviews, streamlining hardware description workflows. The approach demonstrated proficiency in build system configuration and hardware description language, laying a foundation for future codebase cleanup and improved verification practices.