Contributed to the xlsynth/bedrock-rtl repository by developing Burst Equivalents for flow multiplexers, a feature that ensures grants are maintained until the last signal of the granted flow is asserted. This approach prevents interleaving of multi-cycle bursts across different flows, thereby improving the stability and predictability of data handling within the RTL design. The implementation, using SystemVerilog and leveraging expertise in digital design and hardware verification, enhances both reliability and maintainability by introducing explicit burst semantics. The work addressed cross-flow contention and was documented in collaboration with another contributor, reflecting a focused and methodical approach to FPGA development challenges.