During March 2026, Jo Wright developed Burst Equivalents for Flow Multiplexers in the xlsynth/bedrock-rtl repository, focusing on enhancing RTL reliability and data handling predictability. By ensuring that grants are held until the last signal of the granted flow is asserted, Jo’s approach prevented interleaving of multi-cycle bursts across different flows, thereby reducing cross-flow contention. This feature was implemented using SystemVerilog and leveraged skills in digital design and hardware verification. The work introduced explicit burst semantics to the flow multiplexers, resulting in more stable and maintainable FPGA designs. The depth of the solution addressed both stability and maintainability concerns.