During October 2024, Demin Han focused on enhancing the OpenXiangShan/riscv-isa-sim repository by addressing a critical issue in RISC-V interrupt handling within the simulator. He identified and corrected a bit shift error in the interrupt enable logic, which previously caused incorrect starting positions for non-standard interrupts. Using C++ and leveraging his expertise in embedded systems and low-level programming, Demin implemented the fix to ensure accurate interrupt priority handling and improved simulation fidelity. The solution was validated through targeted tests and code review, reducing the risk of edge-case failures and increasing the reliability of interrupt-driven workloads in RISC-V simulations.