Purdue-SoCET/tensor-core
Oct 2025 – Oct 2025
1 Month active
Languages Used
SystemVerilog
Technical Skills
Digital Logic DesignFPGA DevelopmentHardware DesignRTL DesignVerilog/SystemVerilog
Duc Pham
PROFILE
Duc Pham
Developed a hardware accelerator for the Purdue-SoCET/tensor-core repository, focusing on enhancing data batching and processing throughput. Designed and implemented the Batcher Xbar module using a pipelined compare-and-swap architecture to efficiently sort and batch data within the tensor-core stack. Employed SystemVerilog and RTL design principles to ensure robust hardware functionality, and created a dedicated testbench to validate both standard operation and edge-case scenarios during verification. The work demonstrated a complete feature development cycle, from architectural design through verification, and reinforced best practices in hardware-software integration using digital logic design and FPGA development methodologies for future integration testing.
Overall Statistics
Feature vs Bugs
100%Features
Repository Contributions
1Total
Bugs
0
Commits
1
Features
1
Lines of code
283
Activity Months1
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Work History
October 2025
1 Commits • 1 Features
Oct 1, 2025October 2025 monthly summary for Purdue-SoCET/tensor-core. Deliverables focused on hardware acceleration to boost data batching/processing throughput with verification coverage.
1 Commits • 1 Features
Oct 1, 2025October 2025 monthly summary for Purdue-SoCET/tensor-core. Deliverables focused on hardware acceleration to boost data batching/processing throughput with verification coverage.
October 2025
Activity
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Quality Metrics
Correctness90.0%
Maintainability80.0%
Architecture90.0%
Performance90.0%
AI Usage20.0%
Skills & Technologies
Programming Languages
SystemVerilog
Technical Skills
Digital Logic DesignFPGA DevelopmentHardware DesignRTL DesignVerilog/SystemVerilog
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