During September 2025, Maniananth developed advanced GPU memory bandwidth models to enhance performance and cost estimation for H100 GPUs. In the Intel-tensorflow/tensorflow repository, he implemented a dynamic HBM bandwidth model for dot fusion, introducing a DMA-size-based effective bandwidth function and a lookup table to replace hardcoded device checks, increasing model flexibility. He also contributed to Intel-tensorflow/xla by integrating an HBM derate curve and refactoring time calculations to use lookup tables, improving accuracy for memory-bound workloads. His work, primarily in C++ and CUDA, demonstrated depth in GPU programming and performance optimization, supporting future architectural extensions and robust test coverage.