Worked on a backend instruction dispatch overhaul for the OpenXiangShan/XiangShan repository, focusing on improving maintainability and stability in hardware design. The approach involved replacing the DynInst mechanism with EnqRobUop across core dispatch components to standardize and stabilize instruction handling. Initialization logic was clarified by moving from broad assignments to explicit field-by-field initialization, reducing potential hazards. Duplicate imports and redundant dispatch items were removed to enhance code cleanliness and reduce regression risk. The work spanned multiple Scala modules, leveraging skills in backend development and hardware description languages to deliver targeted, commit-driven improvements without introducing new bugs during the development period.