Over a two-month period, this developer enhanced RISC-V cryptographic and benchmarking capabilities across riscv/sdtrigpend and pq-code-package/mlkem-c-aarch64. They clarified security documentation by refining explanations of instruction timing risks in scalar cryptography, improving technical writing for clearer guidance. In pq-code-package/mlkem-c-aarch64, they introduced RISC-V Vector Extension support by integrating new C and assembly code, compiler flags, and Makefile updates, enabling vectorized performance gains. Additionally, they implemented direct cycle counting via PMU access for both 32-bit and 64-bit RISC-V, expanding benchmarking coverage. Their work demonstrated expertise in embedded systems, low-level programming, and performance optimization using C and assembly.