Worked on enhancing reliability and test coverage for the I3C core by developing a dedicated bus idle state timer coverage test in the chipsalliance/i3c-core repository. Focused on system design and verification, the work addressed coverage gaps in idle-state handling and timer behavior, reducing production timing risks. Leveraging Python and test automation techniques, the new test suite enabled earlier detection of timing and regression issues, contributing to improved maintainability. The implementation validated critical aspects of the I3C protocol, ensuring robust handling of bus idle states and timers, and expanded the overall validation framework for ongoing hardware verification efforts.