During May 2025, Alejandro developed a VHDL testbench for the InvSubBytes module in the Matziaz/TE2002B repository, focusing on establishing early verification coverage before synthesis. He implemented stimulus generation with clock and enable signals, validating functional behavior through a targeted test case. This work leveraged his skills in digital design, hardware description language, and testbench development, resulting in a version-controlled verification asset that reduces integration risk and accelerates future verification cycles. By laying the groundwork for automated regression and feature verification, Alejandro’s contribution provided a robust foundation for ongoing hardware validation, though the scope was limited to a single feature.