Developed a VHDL testbench for the InvSubBytes module in the Matziaz/TE2002B repository, focusing on establishing early verification coverage prior to synthesis. The testbench was designed to drive stimulus using clock and enable signals, validating functional behavior through a single targeted test case. This approach reduced integration risk and accelerated verification cycles by providing a foundation for future regression testing. The work demonstrated skills in digital design, hardware description language, and testbench development, with all verification assets version-controlled for maintainability. No major bug fixes were required during this period, reflecting a focus on proactive verification rather than reactive debugging.