
Shriya Balu developed a GPS-based time synchronization feature for the PurdueElectricRacing/firmware repository, focusing on enhancing timing accuracy and data integrity in embedded systems. Using C programming and firmware development skills, Shriya implemented a pathway that updates the Data Acquisition (DAQ) system’s Real-Time Clock (RTC) with GPS time, ensuring synchronized data logging across the system. The work included end-to-end validation of the GPS timestamp flow, from source to RTC update and data logs, and comprehensive documentation to support deployment readiness. This feature addressed the challenge of precise timekeeping in real-time systems, demonstrating depth in embedded and real-time firmware engineering.
March 2026: PurdueElectricRacing/firmware focused on DAQ system cleanup and refactoring to improve maintainability and future feature velocity. Delivered targeted code cleanup and DAQ hub restructuring with a single, well-documented commit.
March 2026: PurdueElectricRacing/firmware focused on DAQ system cleanup and refactoring to improve maintainability and future feature velocity. Delivered targeted code cleanup and DAQ hub restructuring with a single, well-documented commit.
February 2026: Delivered a major DAQ subsystem redesign for PurdueElectricRacing/firmware, implementing a lockless single-producer/multiple-consumer (SPMC) architecture to optimize CAN data handling, SD logging, and Ethernet UDP streaming. Removed legacy TCP code to streamline the data path, and enabled 4-bit SDIO transfers to improve throughput. The SD logging thread now blocks on DMA writes to maximize data transfer efficiency, with the SD logging path thoroughly tested. Business value includes higher telemetry bandwidth, more reliable streaming to SD/UDP endpoints, and reduced CPU overhead. Commit 40e15a7d2ec1132e1ba8fe6778aba86cf56dc2ac (DAQ Redesign with Lockless SPMC) with co-authored-by Irving Wang.
February 2026: Delivered a major DAQ subsystem redesign for PurdueElectricRacing/firmware, implementing a lockless single-producer/multiple-consumer (SPMC) architecture to optimize CAN data handling, SD logging, and Ethernet UDP streaming. Removed legacy TCP code to streamline the data path, and enabled 4-bit SDIO transfers to improve throughput. The SD logging thread now blocks on DMA writes to maximize data transfer efficiency, with the SD logging path thoroughly tested. Business value includes higher telemetry bandwidth, more reliable streaming to SD/UDP endpoints, and reduced CPU overhead. Commit 40e15a7d2ec1132e1ba8fe6778aba86cf56dc2ac (DAQ Redesign with Lockless SPMC) with co-authored-by Irving Wang.
January 2026 focused on improving timing accuracy and data integrity for PurdueElectricRacing/firmware by delivering GPS-based time synchronization for the DAQ RTC. Completed end-to-end validation of the GPS-timestamp pathway and prepared for deployment to ensure synchronized data logging across the system.
January 2026 focused on improving timing accuracy and data integrity for PurdueElectricRacing/firmware by delivering GPS-based time synchronization for the DAQ RTC. Completed end-to-end validation of the GPS-timestamp pathway and prepared for deployment to ensure synchronized data logging across the system.

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