During March 2026, Ameba0422 contributed to the filipnavara/runtime repository by implementing RISC-V instruction printing in JIT dumps during the Generate Code phase. This feature, controlled by the JitDump flag, enhanced debugging visibility by displaying RISC-V instructions such as auipc and jalr alongside standard log lines, addressing a previous gap in traceability for generated code. Working primarily in C++ and leveraging expertise in RISC-V architecture and compiler design, Ameba0422 documented current limitations, such as unresolved jump offsets, and collaborated across teams to integrate the feature. The work demonstrated depth in low-level programming and improved codegen instrumentation for RISC-V targets.