OpenXiangShan/GEM5
Jul 2026 – Jul 2026
1 Month active
Languages Used
No languages
Technical Skills
C++Compiler OptimizationComputer ArchitectureMemory ManagementRISC-V ArchitectureRISC-V ISA
Tao Shuo
PROFILE
Tao Shuo
Worked on enhancing the memory subsystem correctness and robustness for the RISC-V backend in the OpenXiangShan/GEM5 repository, focusing on virtual memory translation stability. Addressed two critical bugs by improving L1 TLB compression logic, introducing normalized address comparisons aligned with the TLB trie key, and adding defensive checks to prevent invalid entry updates. Refined refill handling to reduce translation misses and reinforced safeguards for correct alias management. Additionally, resolved undefined behavior in word-level arithmetic by applying unsigned arithmetic with explicit 32-bit sign extension, ensuring modulo-2^32 semantics. Utilized C++, RISC-V ISA, and memory management expertise throughout the process.
Overall Statistics
Feature vs Bugs
0%Features
Repository Contributions
2Total
Bugs
2
Commits
2
Features
0
Lines of code
116
Activity Months1
Your Network
71 peopleSame Organization
@mails.tsinghua.edu.cn37
Work History
July 2026
2 Commits
Jul 1, 2026July 2026 highlights focus on memory subsystem correctness and robustness for the RISC-V backend in OpenXiangShan/GEM5. Key delivery includes L1 TLB compression correctness improvements with normalized address comparisons aligned to the TLB trie key, improved refill handling, and defensive checks to prevent invalid compressed entry updates. Also fixed undefined behavior in word-level arithmetic by using unsigned arithmetic with explicit 32-bit sign extension to preserve modulo-2^32 semantics. These changes reduce post-refill translation misses, tighten memory translation correctness, and reinforce safety under optimization. Technologies/skills demonstrated include RISC-V memory subsystem design, TLB/PTW internals, address normalization (buildKey domain), unsigned arithmetic and sign-extension techniques, and defensive programming practices. Business value: higher stability in virtual memory translation, fewer debugging cycles, and safer arithmetic under optimization, enabling more reliable performance tuning and deployment.
2 Commits
Jul 1, 2026July 2026 highlights focus on memory subsystem correctness and robustness for the RISC-V backend in OpenXiangShan/GEM5. Key delivery includes L1 TLB compression correctness improvements with normalized address comparisons aligned to the TLB trie key, improved refill handling, and defensive checks to prevent invalid compressed entry updates. Also fixed undefined behavior in word-level arithmetic by using unsigned arithmetic with explicit 32-bit sign extension to preserve modulo-2^32 semantics. These changes reduce post-refill translation misses, tighten memory translation correctness, and reinforce safety under optimization. Technologies/skills demonstrated include RISC-V memory subsystem design, TLB/PTW internals, address normalization (buildKey domain), unsigned arithmetic and sign-extension techniques, and defensive programming practices. Business value: higher stability in virtual memory translation, fewer debugging cycles, and safer arithmetic under optimization, enabling more reliable performance tuning and deployment.
July 2026
Activity
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Quality Metrics
Correctness100.0%
Maintainability80.0%
Architecture100.0%
Performance80.0%
AI Usage60.0%
Skills & Technologies
Programming Languages
No languages yet
Technical Skills
C++Compiler OptimizationComputer ArchitectureMemory ManagementRISC-V ArchitectureRISC-V ISATLB Optimization
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