Worked on enhancing the reliability of hardware verification for the pulp-platform/croc repository, focusing on the JTAG testbench. Addressed a critical issue in SystemVerilog by refining the read-back verification logic to use strict inequality, which prevents false positives and negatives during JTAG debugging. This adjustment improved the accuracy of regression tests and reduced flaky outcomes in continuous integration pipelines. The solution also resolved a fatal error in the testbench when handling undefined values, leading to more stable hardware bring-up. Throughout the process, maintained clear commit traceability and applied expertise in hardware verification and JTAG debugging to ensure robust validation workflows.