Yuyake worked on upstream integration of the CoupledL2 module for the OpenXiangShan/HBL2 repository, focusing on aligning with the latest xs/master branch to enhance stability and performance. Using Chisel and Scala, Yuyake improved clock gating and memory management within CoupledL2, optimizing power efficiency and memory handling. The work included MMIO bridge performance tuning, refined prefetch statistics, and critical path timing fixes in the MainPipe, all aimed at reducing divergence from upstream and improving predictability for silicon validation. This engineering effort demonstrated depth in FPGA and hardware design, addressing both functional enhancements and subtle timing and observability challenges.