Worked on upstream integration of the CoupledL2 module for the OpenXiangShan/HBL2 repository, focusing on aligning with the latest xs/master branch to enhance stability and performance. Leveraged Chisel and Scala to implement improved clock gating and memory management, optimizing power efficiency and memory handling within the module. Addressed MMIO bridge performance by increasing bridge size and tuning timing parameters, while refining prefetch statistics and monitoring for better observability. Resolved several critical path timing and logic issues in the MainPipe, reducing divergence from upstream and improving predictability for silicon validation and production workflows in advanced FPGA and hardware design contexts.