Worked on the OpenXiangShan/riscv-isa-sim repository, focusing on improving code quality within embedded systems projects. Addressed a documentation bug by standardizing the formatting of RISC-V instruction definition comments, specifically correcting spacing around commas in mnemonics to align with established coding style guidelines. This cleanup enhanced the readability and maintainability of the codebase, making it easier for future contributors to understand and review instruction definitions. Utilized C and RISC-V assembly skills to ensure that the changes integrated smoothly with the existing code structure. The work emphasized precise commit messaging and contributed to more effective Git-based change tracking and code review.