Worked on stabilizing the floating-point unit (FPU) model path in the ucb-bar/chipyard repository, focusing on resolving memory modeling issues under multi-threaded conditions. Addressed a critical bug by temporarily disabling FPU model optimizations, specifically by commenting out a line related to register file annotation, which helped maintain core functionality and reduce test flakiness. Documented the rationale and added a clear TODO for future re-enablement of optimizations, ensuring traceability and compliance. Utilized skills in FPGA development and hardware design, with Scala as the primary language, to support ongoing stability while planning for a more robust optimization approach in subsequent sprints.