Rice-MECE-Capstone-Projects/SwitchMCU
Feb 2025 – May 2025
3 Months active
Languages Used
PythonSystemVerilogVerilog
Technical Skills
Computer ArchitectureDigital Logic DesignHardware DesignPython ScriptingRISC-VRISC-V Architecture
Ben Wilson
PROFILE
Ben Wilson
During three months on the Rice-MECE-Capstone-Projects/SwitchMCU repository, Benji Wang developed and enhanced a RISC-V processor core, focusing on modularity, correctness, and verification. He implemented BRAM-based instruction memory, expanded decode and execute modules, and introduced a memory-request state machine to improve subsystem reliability. Using Verilog, SystemVerilog, and Python, Benji built integrated testbenches and a UVM-based coverage reporting system, enabling thorough validation and coverage analysis. His work addressed signed operand handling, modularized core components, and streamlined integration with SOC flows. These contributions improved maintainability, accelerated feature delivery, and reduced verification risk, demonstrating depth in digital design and hardware verification.
Overall Statistics
Feature vs Bugs
60%Features
Repository Contributions
5Total
Bugs
2
Commits
5
Features
3
Lines of code
85,206
Activity Months3
Your Network
30 peopleSame Organization
@rice.edu21
Shared Repositories
9
Bruce TMember
Ithzel ToscanoMember
juan GarzaMember
Kelly C.Member
Chenran75Member
lindseyr23Member
Lindsey RussMember
adidokkMember
Varun SanthoshMember
Work History
May 2025
2 Commits • 2 Features
May 1, 2025May 2025 performance-review-ready summary for Rice-MECE-Capstone-Projects/SwitchMCU: Focused on delivering core feature enhancements and a robust verification framework. The work improves processor capabilities, memory subsystem reliability, and verification visibility, delivering business value through higher quality releases and faster validation cycles.
2 Commits • 2 Features
May 1, 2025May 2025 performance-review-ready summary for Rice-MECE-Capstone-Projects/SwitchMCU: Focused on delivering core feature enhancements and a robust verification framework. The work improves processor capabilities, memory subsystem reliability, and verification visibility, delivering business value through higher quality releases and faster validation cycles.
May 2025
March 2025
1 Commits
Mar 1, 2025March 2025 monthly summary for Rice-MECE-Capstone-Projects/SwitchMCU focusing on correctness and testability. Delivered fixes to signed operand handling in the execute unit and introduced modular wrappers and a top-level test harness to enable modular testing and end-to-end validation of the instruction processing pipeline. These changes improve reliability, maintainability, and speed of future feature work.
March 2025
1 Commits
Mar 1, 2025March 2025 monthly summary for Rice-MECE-Capstone-Projects/SwitchMCU focusing on correctness and testability. Delivered fixes to signed operand handling in the execute unit and introduced modular wrappers and a top-level test harness to enable modular testing and end-to-end validation of the instruction processing pipeline. These changes improve reliability, maintainability, and speed of future feature work.
February 2025
2 Commits • 1 Features
Feb 1, 2025February 2025 monthly summary for Rice-MECE-Capstone-Projects/SwitchMCU: Delivered foundational test scaffolding for the Core Decode Module and completed a targeted bug fix with a modular architecture upgrade. The work established verifiable core functionality, improved decode interaction testing, and introduced a top-level execute+decode wrapper, strengthening modularity and future integration. This enhances reliability, accelerates feature delivery, and demonstrates proficiency in Verilog-based design, SWC module interactions, and digital design best practices.
2 Commits • 1 Features
Feb 1, 2025February 2025 monthly summary for Rice-MECE-Capstone-Projects/SwitchMCU: Delivered foundational test scaffolding for the Core Decode Module and completed a targeted bug fix with a modular architecture upgrade. The work established verifiable core functionality, improved decode interaction testing, and introduced a top-level execute+decode wrapper, strengthening modularity and future integration. This enhances reliability, accelerates feature delivery, and demonstrates proficiency in Verilog-based design, SWC module interactions, and digital design best practices.
February 2025
Activity
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Quality Metrics
Correctness76.0%
Maintainability76.0%
Architecture76.0%
Performance64.0%
AI Usage28.0%
Skills & Technologies
Programming Languages
PythonSystemVerilogVerilog
Technical Skills
Computer ArchitectureDigital DesignDigital Logic DesignHardware DesignHardware VerificationPython ScriptingRISC-VRISC-V ArchitectureRTL DesignSystemVerilogTest AutomationTestbench DevelopmentUVMVerificationVerilog
Repositories Contributed To
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