Rice-MECE-Capstone-Projects/SwitchMCU
Feb 2025 – Apr 2025
2 Months active
Languages Used
VerilogMakefilePythonSystemVerilog
Technical Skills
Computer ArchitectureDigital Logic DesignHardware DesignBranch PredictionDigital DesignPipeline Design
lindseyr23
PROFILE
Lindseyr23
Developed and refined a branch prediction module for the RISC-V processor within the Rice-MECE-Capstone-Projects/SwitchMCU repository, focusing on improving instruction fetch efficiency and reducing pipeline stalls. The work involved implementing static, 1-bit, and 2-bit prediction schemes in Verilog, with update logic driven by actual branch outcomes. Enhancements included addressing a timing bug and strengthening the Python-based test harness to quantify false predictions, enabling targeted tuning and more reliable performance profiling. The contributions established a robust foundation for dynamic predictor evaluation and further performance optimization, leveraging skills in computer architecture, RTL design, and test automation over a focused two-month period.
Overall Statistics
Feature vs Bugs
100%Features
Repository Contributions
4Total
Bugs
0
Commits
4
Features
2
Lines of code
2,821
Activity Months2
Your Network
9 peopleShared Repositories
9
Ben WilsonMember
Bruce TMember
Ithzel ToscanoMember
juan GarzaMember
Kelly C.Member
Chenran75Member
Lindsey RussMember
adidokkMember
Varun SanthoshMember
Work History
April 2025
3 Commits • 1 Features
Apr 1, 2025April 2025: Focused on delivering and refining the RISC-V Branch Prediction module for SwitchMCU, addressing a timing bug and strengthening the test harness to quantify false predictions for targeted tuning. Delivered integrated feature with improved evaluation feedback, contributing to higher instruction fetch efficiency and more reliable performance profiling.
3 Commits • 1 Features
Apr 1, 2025April 2025: Focused on delivering and refining the RISC-V Branch Prediction module for SwitchMCU, addressing a timing bug and strengthening the test harness to quantify false predictions for targeted tuning. Delivered integrated feature with improved evaluation feedback, contributing to higher instruction fetch efficiency and more reliable performance profiling.
April 2025
February 2025
1 Commits • 1 Features
Feb 1, 2025February 2025 monthly summary for Rice-MECE-Capstone-Projects/SwitchMCU. Delivered a Branch Prediction Module for the RISC-V Processor in Verilog, with static, 1-bit, and 2-bit schemes, updating predictions based on actual outcomes to reduce stalls and improve instruction fetch efficiency. The change is tracked under commit 3ecbdfc3b3ba535edad666216a13ed6b0976bc0e. This work establishes a foundation for dynamic tuning, performance optimization, and RTL verification across the SwitchMCU project.
February 2025
1 Commits • 1 Features
Feb 1, 2025February 2025 monthly summary for Rice-MECE-Capstone-Projects/SwitchMCU. Delivered a Branch Prediction Module for the RISC-V Processor in Verilog, with static, 1-bit, and 2-bit schemes, updating predictions based on actual outcomes to reduce stalls and improve instruction fetch efficiency. The change is tracked under commit 3ecbdfc3b3ba535edad666216a13ed6b0976bc0e. This work establishes a foundation for dynamic tuning, performance optimization, and RTL verification across the SwitchMCU project.
Activity
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Quality Metrics
Correctness80.0%
Maintainability80.0%
Architecture70.0%
Performance70.0%
AI Usage20.0%
Skills & Technologies
Programming Languages
MakefilePythonSystemVerilogVerilog
Technical Skills
Branch PredictionComputer ArchitectureDigital DesignDigital Logic DesignHardware DesignPipeline DesignPython ScriptingRISC-VRISC-V ArchitectureRTL DesignTest AutomationVerilog
Repositories Contributed To
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