Purdue-SoCET/RISCVBusiness
May 2025 – Oct 2025
2 Months active
Languages Used
CC++MakefilePythonShellSystemVerilogTextVerilog
Technical Skills
Assembly LanguageBuild System ManagementBuild SystemsC++Cache CoherenceCode Cleanup
Cole Nelson
PROFILE
Cole Nelson
Worked on the Purdue-SoCET/RISCVBusiness repository, developing and refining RISC-V CPU infrastructure with a focus on RV32C decompression, test automation, and architectural simplification. Built a robust RV32C development and testing pipeline using SystemVerilog and C++, introducing decode, decompressor, and testbench modules while improving repository cleanliness and tooling. Enhanced reliability by fixing decompressor hint encodings, stabilizing integration tests, and updating licensing. Later, removed the RISC-MGMT module and unused extensions, simplifying the core architecture and reducing maintenance. Addressed multicore interrupt handling and CPU tracker output, leveraging Verilog and low-level debugging skills to improve correctness, reliability, and future development efficiency.
Overall Statistics
Feature vs Bugs
43%Features
Repository Contributions
27Total
Bugs
8
Commits
27
Features
6
Lines of code
10,902
Activity Months2
Your Network
133 peopleShared Repositories
5
Work History
October 2025
4 Commits • 1 Features
Oct 1, 2025October 2025: Key architectural simplification and reliability improvements in Purdue-SoCET/RISCVBusiness. Delivered removal of the RISC-MGMT module and associated extensions, updated the pipeline wrapper and core modules to reflect the simplified architecture, reducing maintenance burden and unused components (CRC32 and RV32M). Fixed critical CPU-tracker mnemonics printing and unified interrupt handling timing and CSR setup, reducing race conditions and improving correctness across multicore operation. These changes improve system reliability, reduce debugging time, and streamline future feature work.
4 Commits • 1 Features
Oct 1, 2025October 2025: Key architectural simplification and reliability improvements in Purdue-SoCET/RISCVBusiness. Delivered removal of the RISC-MGMT module and associated extensions, updated the pipeline wrapper and core modules to reflect the simplified architecture, reducing maintenance burden and unused components (CRC32 and RV32M). Fixed critical CPU-tracker mnemonics printing and unified interrupt handling timing and CSR setup, reducing race conditions and improving correctness across multicore operation. These changes improve system reliability, reduce debugging time, and streamline future feature work.
October 2025
May 2025
23 Commits • 5 Features
May 1, 2025May 2025 performance summary for Purdue-SoCET/RISCVBusiness. Delivered a robust RV32C development and testing pipeline, completed significant repository cleanliness and tooling improvements, and fixed critical bugs, resulting in increased reliability, faster iteration cycles, and broader RISCV testing coverage.
May 2025
23 Commits • 5 Features
May 1, 2025May 2025 performance summary for Purdue-SoCET/RISCVBusiness. Delivered a robust RV32C development and testing pipeline, completed significant repository cleanliness and tooling improvements, and fixed critical bugs, resulting in increased reliability, faster iteration cycles, and broader RISCV testing coverage.
Activity
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Quality Metrics
Correctness90.8%
Maintainability86.4%
Architecture85.6%
Performance81.4%
AI Usage20.0%
Skills & Technologies
Programming Languages
AssemblyCC++MakefilePythonShellSystemVerilogTextVerilogYAML
Technical Skills
Assembly LanguageBuild System ManagementBuild SystemsC++CPU ArchitectureCache CoherenceCode CleanupCompiler CompatibilityCompiler DevelopmentConfiguration ManagementDebuggingDigital DesignDigital Logic DesignEmbedded SystemsHardware Description Language
Repositories Contributed To
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