Worked on enhancing callback lifecycle management in the antmicro/verilator repository, focusing on improving simulation stability and maintainability. Addressed a bug by introducing a dedicated m_cbCallList to track active callbacks, refactoring the removal logic to ensure callbacks are invalidated and removed properly, and preventing stale references. Added comprehensive regression tests to verify correct behavior across various scenarios, ensuring robust cleanup and reducing the risk of crashes or inconsistent states during simulation. Utilized C++ and applied skills in callback management, regression testing, and VPI integration, delivering a targeted fix that improved the correctness and reliability of callback handling in Verilog simulations.