Worked on the CS350C-SP25/ozone-processor repository to refactor the instruction scheduler, focusing on managing per-unit instruction queues to enhance throughput and resource utilization. The approach involved expanding scheduler capacity and integrating the reorder buffer (ROB) for end-to-end instruction flow, including enqueueing from the ROB, dequeuing when functional units became available, and signaling execution completion back to the ROB. This SystemVerilog-based work addressed scheduling bottlenecks and established a foundation for future parallelism improvements. Leveraging skills in computer architecture, digital logic design, and hardware design, the changes improved scheduling predictability and throughput without introducing new bug fixes during the development period.