EXCEEDS logo
Exceeds
Lorenzo Leone

PROFILE

Lorenzo Leone

Worked on the pulp-platform/picobello and related repositories to deliver scalable hardware features and robust memory subsystem enhancements. Developed configurable memory architectures, including Scratchpad Memory tiles and end-to-end multicast support, by integrating SystemVerilog and C++ for hardware-software co-design. Improved CI/CD pipelines and dependency management to ensure reliable validation and compatibility across RISC-V based systems. Addressed hardware resource identification and memory bandwidth issues, enabling efficient system integration and deployment. Contributed to the pulp-platform/cheshire repository by implementing optional DRAM integration and reorganizing project structure for maintainability. Demonstrated expertise in embedded systems, build systems, and test development to support platform scalability.

Overall Statistics

Feature vs Bugs

80%Features

Repository Contributions

12Total
Bugs
2
Commits
12
Features
8
Lines of code
44,572
Activity Months5

Work History

April 2026

1 Commits • 1 Features

Apr 1, 2026

April 2026 monthly summary for pulp-platform/cheshire focusing on delivering a configurable DRAM integration path, stabilizing VIP interactions, and improving project maintainability to accelerate Cheshire platform bring-up.

July 2025

2 Commits • 1 Features

Jul 1, 2025

July 2025 performance summary: Delivered key memory subsystem enhancements in pulp-platform/picobello, focusing on scalable memory architectures and memory access efficiency. Implemented new Scratchpad Memory (SPM) Tiles with Narrow and Wide Top-Level Variants and a 256 KiB hardware tile, including configuration updates, hardware instantiation, and software tests verifying access to the new memory regions. Also fixed critical memory bandwidth issues by updating dependencies and hardware configurations, disabling HideStrb in axi_obi, and adjusting MaxTrans to reflect OBI latency. These changes collectively improve throughput, reliability, and scalability of the memory subsystem, enabling broader deployment of SPM tiles and better support for performance-critical workloads.

June 2025

5 Commits • 3 Features

Jun 1, 2025

June 2025 monthly summary: Delivered end-to-end Picobello Multicast feature across hardware, packaging, tests, and CI, including NoC changes and packaging definitions, with dependency updates (FloO_NoC and common_cells) to support synthesis and routing improvements. Added advanced multicast tests and CI integration to validate end-to-end functionality. Snitch Picobello test suite build was aligned with current C++/LLVM toolchains by updating build configurations and LLVM path handling to resolve compatibility issues. In snitch_cluster, MemoryDumpReader was added to verif_utils to enable verification without IPC, with CLI options --no-ipc, --memdump, and --memaddr. Notable commits include 911b723 (hw: Add multicast support), aae8fe12 (test: Advanced multicast tests), 44860c89 (deps: Clean common_cells dependency), 12ee0440b8 (hw: Fix some 🐛), and 514e0929 (util: Extend verif_utils to support testbenches without IPC interface).

May 2025

2 Commits • 1 Features

May 1, 2025

Monthly work summary for 2025-05 highlighting key deliverables across pulp-platform/picobello and pulp-platform/snitch_cluster. Focused on hardware design accuracy, system-wide multicast capabilities, and CI/CD improvements that deliver business value and robust technical foundations.

April 2025

2 Commits • 2 Features

Apr 1, 2025

April 2025 (2025-04) monthly summary for pulp-platform/picobello: Delivered two high-impact features that strengthen reliability and scalability across architectures, with accompanying CI and configurability improvements. Key outcomes include robust memory validation and a flexible system parametrization framework that supports multi-architecture builds.

Activity

Loading activity data...

Quality Metrics

Correctness87.6%
Maintainability81.6%
Architecture85.0%
Performance79.2%
AI Usage23.4%

Skills & Technologies

Programming Languages

CC++HjsonMakefilePythonShellSystemVerilogYAML

Technical Skills

Build System ManagementBuild SystemsC ProgrammingC++ DevelopmentCI/CDDependency ManagementEmbedded SystemsFPGA/ASIC DevelopmentHardware DesignHardware TestingHardware VerificationMemory ManagementMulticast CommunicationNetwork-on-Chip (NoC)Python Scripting

Repositories Contributed To

3 repos

Overview of all repositories you've contributed to across your timeline

pulp-platform/picobello

Apr 2025 Jul 2025
4 Months active

Languages Used

CHjsonMakefileSystemVerilogYAMLC++Shell

Technical Skills

Build System ManagementCI/CDEmbedded SystemsFPGA/ASIC DevelopmentHardware DesignHardware Testing

pulp-platform/snitch_cluster

May 2025 Jun 2025
2 Months active

Languages Used

CShellSystemVerilogPython

Technical Skills

CI/CDEmbedded SystemsHardware DesignRISC-V ArchitectureSystem IntegrationHardware Verification

pulp-platform/cheshire

Apr 2026 Apr 2026
1 Month active

Languages Used

CC++

Technical Skills

RISC-V architectureSystemVerilogembedded systemshardware design