Worked on the antmicro/verilator repository to implement support for Verilog 'union soft' declarations, enhancing the tool’s language coverage and model reliability. This involved updating the abstract syntax tree and parser to recognize the 'union soft' keyword and handle packed unions of varying sizes, using C++ and Verilog HDL. Expanded the test suite to cover new cases and improved error reporting for invalid hard packed unions, ensuring compatibility with existing workflows. The work focused on AST manipulation and compiler design, enabling more accurate hardware modeling and reducing downstream debugging time for users working with complex SystemVerilog and Verilog codebases.