Worked on enhancing the Verilog resetall directive within the antmicro/verilator repository, focusing on improving simulation robustness and completeness. Developed lexer-level changes in Verilog to ensure resetall properly initializes simulation time, disables cell defines, and sets unconnected drive options, directly impacting how reset behavior is processed during simulation. This approach reduced the need for workaround configurations and improved the reliability of Verilog test benches. Leveraged skills in lexer development and Verilog simulation to address internal tracking requirements, delivering a targeted feature that strengthened resetall handling. The work demonstrated depth in language-specific parsing and simulation control within hardware description workflows.