Worked on the antmicro/verilator repository to enhance the coverage analysis tool by implementing expression coverage for continuous assignment statements. This feature improved the ability to track and report on expression evaluations during simulation, providing deeper insight into RTL logic validation. The approach involved C++ development and integration with existing code coverage analysis workflows, ensuring that coverage data now includes a broader range of simulation behaviors. Leveraging skills in software testing and Verilog, the work focused on instrumentation and seamless tooling integration. The contribution addressed a specific gap in coverage reporting, supporting more thorough verification processes within the Verilator ecosystem.