In May 2025, Zhou Zhirong addressed a critical timing issue in the OpenXiangShan-Nanhu/Nanhu-V5 repository by implementing a targeted fix for PTW-PMP synchronization. Using skills in hardware design, low-level programming, and timing analysis, Zhou introduced a one-clock-cycle delay to the Physical Memory Protection request signal, resolving a race condition between the Page Table Walker and PMP modules. This change improved memory access reliability and enhanced overall system stability, reducing the risk of memory-access faults in long-running deployments. The work, developed in Scala, demonstrated careful attention to asynchronous module interaction and contributed to a more robust memory protection path.