Worked on the design phase for the Bank Queue Interface and DDR4 FSM Arbiter within the Purdue-SoCET/aihw-design-logs repository, focusing on RTL design and thorough documentation. Delivered a comprehensive design baseline that details architectural decisions, trade-offs, and future integration goals, supporting improved reliability and throughput in the memory subsystem. Emphasized maintainability and knowledge transfer by documenting design rationale and outlining next steps for verification and testbench alignment. Collaborated closely with the team to ensure the design was ready for integration and early validation. Utilized Markdown for documentation and contributed to a foundation that reduces schedule risk in future development cycles.