Jaylyst completed the design phase for the Bank Queue Interface and DDR4 FSM Arbiter in the Purdue-SoCET/aihw-design-logs repository, focusing on RTL design and thorough documentation. Their work established a clear baseline for integrating these components into the memory subsystem, aiming to improve reliability and deterministic arbitration. Using Markdown for detailed design logs, Jaylyst documented architectural decisions, trade-offs, and future objectives, which supports maintainability and knowledge transfer. The approach emphasized team collaboration and set the stage for upcoming verification and testbench development. This milestone reduced schedule risk by enabling earlier validation and provided a solid foundation for subsequent engineering efforts.