In March 2025, Saha contributed to the Purdue-SoCET/tensor-core repository by developing two core hardware features focused on control flow and fetch coordination. Saha implemented a conditional enable signal for the branch target buffer update path, refining branch unit behavior and ensuring updates only occur when appropriate. Additionally, Saha introduced a freeze signal to the fetch interface, allowing the program counter to pause advancement during stalls for safer instruction fetch handling. These changes, built using SystemVerilog and grounded in digital logic and hardware design principles, improved the predictability and reliability of branch handling without introducing new bugs, demonstrating careful, traceable engineering.