During November 2024, Socet139 developed a centralized type definition module for the Purdue-SoCET/tensor-core repository, introducing the cpu_types.vh Verilog header. This work focused on consolidating CPU-related parameters such as word width, instruction formats, opcodes, function codes, ALU operations, and cache address formats into a single, reusable file. By applying digital design principles and leveraging SystemVerilog, Socet139 improved code organization and maintainability across the project. The architectural cleanup reduced duplication and streamlined integration of CPU components, laying a stronger foundation for future development. No major bugs were addressed, as the emphasis remained on modularization and standardization of core definitions.