During October 2025, this developer contributed to the Purdue-SoCET/tensor-core repository by designing and implementing the Scratchpad Memory Frontend in SystemVerilog, focusing on hardware and RTL design. They established a modular frontend module with request and response latching, initializing it with clock and reset connections and aligning its latching mechanism to the fvif interface signals for synchronized data flow. Their work included preparing integration with a frontend_vc placeholder, laying the foundation for future arbitration and memory access transformations. This approach enabled safer evolution of the scratchpad subsystem, supporting future performance optimizations and maintainable memory access paths within the project.